Course: EE671: VLSI Design (Autumn 2025)
Instructor: Prof. Laxmeesha Somappa

Our team designed three standard cells — a buffer (BUF), a positive-edge triggered D flip-flop (DF-XTP), and a 2-input AND gate with an inverted input (AND2B) — from transistor-level schematics all the way to verified layouts using the SkyWater 130nm open-source PDK. Each cell was laid out in Magic VLSI following the PDK’s design rules, then extracted and simulated in NGSpice to generate full Liberty (.lib) characterization across a 7×7 matrix of input slew rates and output capacitances. The deliverables for each cell included a SPICE netlist, layout (.mag), Liberty timing/power tables, LEF abstract, and a Verilog behavioral model.

Repository: github.com/abhineet-agarwal/EE671-Standard-Cell-Library